View ICS557-01_251445.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ICS557-01
PCI-EXPRESS CLOCK SOURCE
Description
The ICS557-01 is a clock chip designed for use in PCI-Express Cards as a clock source. It provides a pair of differential outputs at 100 MHz in a small 8-pin SOIC package. Using ICS' patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces HCSL (Host Clock Signal Level) differential outputs at 100 MHz clock frequency. LVDS signal levels can also be supported via an alternative termination scheme.
Features
* Supports PCI-ExpressTM HCSL Outputs
0.7 V current mode differential pair
* * * * * * * * *
Supports LVDS Output Levels Packaged in 8-pin SOIC Available in Pb (lead) free package Operating voltage of 3.3 V Low power consumption Input frequency of 25 MHz Short term jitter 100 ps (peak-to-peak) Output Enable via pin selection Industrial temperature range available
Block Diagram
VDD
Phase Lock Loop X1 25 MHz crystal /clock X2 Clock Buffer/ Crystal Oscillator
CLK CLK
Crystal Tuning Capacitors
GND
OE
RR(IREF)
MDS 557-01 F I n t e gra te d C i r c u i t S y s t e m s
1
525 Race Stre et, San Jo se, CA 9 5126
Revision 011606 te l (40 8) 2 97-12 01
w w w. i c st . c o m
ICS557-01 PCI-EXPRESS CLOCK SOURCE
Pin Assignment
OE X1 X2 GN D 1 2 3 4 8 7 6 5 V DD CL K CL K I RE F
8 P i n ( 1 5 0 mi l ) S OI C
Pin Descriptions
Pin Number
1
Pin Name
OE
Pin Type
Input
Pin Description
Output Enable signal (H = outputs are enabled, L = outputs are disabled/tristated). Internal pull-up resistor. Crystal or clock input. Connect to a 25 MHz crystal or single ended clock. Crystal Connection. Connect to a parallel mode crystal. Leave floating if clock input. Connect to ground.
2 3 4 5 6 7 8
X1 X2 GND
IREF
Input XO Power
Output A 475 precision resistor connected between this pin and ground establishes the external reference current. Output HCSL differential complementary clock output. Output HCSL differential clock output. Power Connect to +3.3 V.
CLK CLK VDD
MDS 557-01 F In te grated Circuit Systems
2
525 Ra ce Street, San Jose, CA 9512 6
Revision 011606 tel (4 08) 297-1 201
w w w. i c s t . c o m
ICS557-01 PCI-EXPRESS CLOCK SOURCE
Applications Information External Components
A minimum number of external components are required for proper operation.
Output Structures
IREF =2.3 mA 6*IREF
Decoupling Capacitors
Decoupling capacitors of 0.01 F should be connected between VDD and the ground plane (pin 4) as close to the VDD pin as possible. Do not share ground vias between components. Route power from power source through the capacitor pad and then into ICS pin.
Crystal
A 25 MHz fundamental mode parallel resonant crystal with CL = 16 pF should be used. This crystal must have less than 300 ppm of error across temperature in order for the ICS557-01 to meet PCI Express specifications.
R R 475
See Output Termination Sections - Pages 3 ~ 5
Crystal Capacitors
Crystal capacitors are connected from pins X1 to ground and X2 to ground to optimize the accuracy of the output frequency. CL= Crystal's load capacitance in pF Crystal Capacitors (pF) = (CL- 8) * 2 For example, for a crystal with a 16 pF load cap, each external crystal cap would be 16 pF. (16-8)*2=16.
General PCB Layout Recommendations
For optimum device performance and lowest output phase noise, the following guidelines should be observed. 1. Each 0.01F decoupling capacitor should be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias should be used between decoupling capacitor and VDD pin. 3. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces should be routed away from the ICS557-01.This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device.
Current Source (Iref) Reference Resistor - RR
If board target trace impedance (Z) is 50, then RR = 475 (1%), providing IREF of 2.32 mA. The output current (IOH) is equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the ICS557-01 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are shown in detail in the PCI-Express Layout Guidelines section. The ICS557-01can also be configured for LVDS compatible voltage levels. See the LVDS Compatible Layout Guidelines section
MDS 557-01 F In te grated Circuit Systems
3
525 Ra ce Street, San Jose, CA 9512 6
Revision 011606 tel (4 08) 297-1 201
w w w. i c s t . c o m
ICS557-01 PCI-EXPRESS CLOCK SOURCE
PCI-Express Layout Guidelines
Recommendations for Differential Routing as non-coupled 50 ohm trace. as non-coupled 50 ohm trace. as non-coupled 50 ohm trace. Dimension 0.5 0.2 0.2 3 49 Dimension 2 min to 1.8 min to Dimension 0.25 to 0.225 min t
ferential Routing on a Single PCB as coupled microstrip 100 ohm differential trace. as coupled stripline 100 ohm differential trace. ial Routing to a PCI Express Connector as coupled microstrip 100 ohm differential trace. as coupled stripline 100 ohm differential trace.
Figure 1: PCI-Express Device Routing
L1 RS L1' RS
L2 L2' RT L3' RT L3
L4 L4'
ICS557-01 Output Clock
PCI-Express Load or Connector
Typical PCI-Express (HCSL) Waveform
700 mV
0 tOR 0.52 V 0.175 V
500 ps
500 ps
tOF 0.52 V 0.175 V
MDS 557-01 F In te grated Circuit Systems
4
525 Ra ce Street, San Jose, CA 9512 6
Revision 011606 tel (4 08) 297-1 201
w w w. i c s t . c o m
ICS557-01 PCI-EXPRESS CLOCK SOURCE
LVDS Compatible Layout Guidelines
LVDS Recommendations for Differential Routing L1 length, Route as non-coupled 50 ohm trace. L2 length, Route as non-coupled 50 ohm trace. RP RQ RT L3 length, Route as coupled 50 ohm differential trace. L3 length, Route as coupled 50 ohm differential trace. Dimension or Value 0.5 max 0.2 max 100 100 150 Unit inch inch ohm ohm ohm
Figure 3: LVDS Device Routing
L1 RQ L1'
L3 L3'
RP
RT ICS557-01 Clock Output
L2' L2
RT LVDS Device Load
Typical LVDS Waveform
1325 mV
1000 mV tOR 500 ps 500 ps tOF
1250 mV 1150 mV
1250 mV 1150 mV
MDS 557-01 F In te grated Circuit Systems
5
525 Ra ce Street, San Jose, CA 9512 6
Revision 011606 tel (4 08) 297-1 201
w w w. i c s t . c o m
ICS557-01 PCI-EXPRESS CLOCK SOURCE
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-01. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Supply Voltage, VDD, VDDA All Inputs and Outputs Ambient Operating Temperature (commercial) Ambient Operating Temperature (industrial) Storage Temperature Junction Temperature Soldering Temperature ESD Protection (Input) 5.5 V
Rating
-0.5 V to VDD+0.5 V 0 to +70C -40 to +85C -65 to +150C 125C 260C 2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85C Parameter Supply Voltage Input High Voltage
1
Symbol V VIH VIL IIL IDD IDDOE CIN COUT LPIN Rout RPUP
Conditions
Min. 3.135 2.0 VSS-0.3
Typ.
Max. 3.465 VDD +0.3 0.8 5 55 35 7 6 5
Units V V A mA mA pF pF nH k k
Input Low Voltage1 Input Leakage Current2 Operating Supply Current Input Capacitance Output Capacitance Pin Inductance Output Resistance Pull-up Resistor
0 < Vin < VDD With 50 and 2 pF load OE =Low Input pin capacitance Output pin capacitance CLK outputs OE
region.
-5
3.0 60
1 Single edge is monotonic when transitioning through 2 Inputs with pull-ups/-downs are not included.
MDS 557-01 F In te grated Circuit Systems
6
525 Ra ce Street, San Jose, CA 9512 6
Revision 011606 tel (4 08) 297-1 201
w w w. i c s t . c o m
ICS557-01 PCI-EXPRESS CLOCK SOURCE
AC Electrical Characteristics - CLK/CLK
Unless stated otherwise, VDD=3.3 V 5%, Ambient Temperature -40 to +85C Parameter Input Frequency Output Frequency Output High Voltage Output Low Voltage Crossing Point Voltage1,2 Crossing Point Voltage1,2,4 Jitter, Cycle-to-Cycle1,3 Rise Time
1,2 1,2
Symbol
Conditions
Min.
Typ. 25 100
Max.
Units MHz MHz
VOH VOL Absolute Variation over all edges
660 -150 250
700 0 350
850 550 140
mV mV mV mV ps
1,2
100 tOR tOF from 0.175 V to 0.525 V from 0.525 V to 0.175 V 175 175 332 344 700 700 125 45 55 30 30 3.0 3.0
ps ps ps % s s ms ms
Fall Time1,2 Rise/Fall Time Variation1,2 Duty Cycle1,3 Output Enable Time Stabilization Time Spread Change Time
1 2 3 4 5 5
All outputs All outputs tSTABLE From power-up VDD=3.3 V tSPREAD Settling period after spread change
Output Disable Time5
Test setup is RL=50 ohms with 2 pF, RR = 475 (1%). Measurement taken from a single-ended waveform. Measurement taken from a differential waveform. Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal. CLKOUT pins are tri-stated when OE is low asserted. CLKOUT is driven differential when OE is high.
Thermal Characteristics (8-pin SOIC)
Parameter
Thermal Resistance Junction to Ambient
Symbol
JA JA JA JC
Conditions
Still air 1 m/s air flow 3 m/s air flow
Min.
Typ.
150 140 120 40
Max. Units
C/W C/W C/W C/W
Thermal Resistance Junction to Case
MDS 557-01 F In te grated Circuit Systems
7
525 Ra ce Street, San Jose, CA 9512 6
Revision 011606 tel (4 08) 297-1 201
w w w. i c s t . c o m
ICS557-01 PCI-EXPRESS CLOCK SOURCE
Marking Diagram (ICS557M-01)
8 5
Marking Diagram (ICS557MI-01)
8 5
557M-01 ###### YYWW
1 4
1
557MI01 ###### YYWW
4
Marking Diagram (ICS557M-01LF)
8 5
Marking Diagram (ICS557MI-01LF)
8 5
557M-01L ###### YYWW
1 4 1
557MI01L ###### YYWW
4
Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 3. "L" designates Pb (lead) free packaging. 4. Bottom marking: (orgin). Origin = country of origin if not USA.
MDS 557-01 F In te grated Circuit Systems
8
525 Ra ce Street, San Jose, CA 9512 6
Revision 011606 tel (4 08) 297-1 201
w w w. i c s t . c o m
ICS557-01 PCI-EXPRESS CLOCK SOURCE
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters Symbol
8
Inches* Min Max
Min
Max
A A1 B
E H
1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 0
1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 8
.0532 .0040 .013 .0075 .1890 .1497 .2284 .010 .016 0
.0688 .0098 .020 .0098 .1968 .1574 .2440 .020 .050 8
C D E e H h L
INDEX AREA
1.27 BASIC
0.050 BASIC
12 D
*For reference only. Controlling dimensions in mm.
A A1 h x 45 C
-Ce
B SEATING PLANE L
.10 (.004)
C
MDS 557-01 F In te grated Circuit Systems
9
525 Ra ce Street, San Jose, CA 9512 6
Revision 011606 tel (4 08) 297-1 201
w w w. i c s t . c o m
ICS557-01 PCI-EXPRESS CLOCK SOURCE
Ordering Information
Part / Order Number
ICS557M-01 ICS557M-01T ICS557M-01LF ICS557M-01LFT ICS557MI-01 ICS557MI-01T ICS557MI-01LF ICS557MI-01LFT
Marking
See Page 8
Shipping Packaging
Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel Tubes Tape and Reel
Package
8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC
Temperature
0 to +70 C 0 to +70 C 0 to +70 C 0 to +70 C -40 to +85 C -40 to +85 C -40 to +85 C -40 to +85 C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 557-01 F In te grat ed Circuit Syst ems
10
525 Ra ce St reet , San Jose, CA 9512 6
Revision 011606 t el (4 08) 297-1 201
w w w. i c s t . c o m

▲Up To Search▲

Price & Availability of ICS557-01

	To Download ICS557-01 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .